74LV4094 datasheet(2/14 Pages) PHILIPS

Part #	74LV4094

Description	8-stage shift-and-store bus register

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product specification

74LV4094

8-stage shift-and-store bus register

2

1998 Jun 23

853-2078 19619

FEATURES

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between V

CC = 2.7 V and VCC = 3.6 V

• Typical V

OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

Tamb = 25°C

• Typical V

OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,

Tamb = 25°C

• Output capability: standard

• I

CC category: MSI

Applications:

• Serial-to-parallel data conversion

• Remote control holding register

DESCRIPTION

The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT4094.

The 74LV4094 is an 8-stage serial shift register having a storage

latch associated with each stage for strobing data from the serial

input (D) to the parallel buffered 3-State outputs (QP0 to OP7). The

parallel outputs may be connected directly to the common bus lines.

Data is shifted on the positive-going clock (CP) transitions. The data

in each shift register is transferred to the storage register when the

strobe input (STR) is HIGH. Data in the storage register appears at

the outputs whenever the output enable input (OE) signal is HIGH.

Two serial outputs (QS1 and QS2) are available for cascading a

number of 74LV4094 devices. Data is available at QS1 on the

positive-going clock edges to allow high-speed operation in

cascaded systems in which the clock rise time is fast. The same

serial information is available at QS2 on the next negative going

clock edge and is for cascading 74LV4094 devices when the clock

rise time is slow.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

CP to QS1

CP to QS2

CP to QPn

STR to QPn

CL = 15 pF;

VCC = 3.3 V

14

13

18

17

ns

fMAX

Maximum clock frequency

95

MHz

CI

Input capacitance

3.5

pF

CPD

Power dissipation capacitance per gate

VCC = 3.3 V

VI = GND to VCCNO TAG

83

pF

NOTE:

1.

CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL × VCC2 × fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

PKG. DWG. #

16-Pin Plastic DIL

–40

°C to +125°C

74LV4094 N

SOT38-4

16-Pin Plastic SO

–40

°C to +125°C

74LV4094 D

SOT109-1

PIN CONFIGURATION

SV01611

1

2

3

4

5

6

STR

D

CP

QP0

QP1

QP2

VCC

OE

QP4

16

15

14

13

12

11

7

8

GND

QS2

QS1

10

9

QP3

QP5

QP6

QP7

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

1

STR

Strobe input

2

D

Serial input

3

CP

Clock input

4, 5, 6, 7, 14,

13, 12, 11

QP0 to QP7

Parallel outputs

8

GND

Ground (0 V)

9, 10

QS1, QS2

Serial outputs

15

OE

Output enable input

16

VCC

Positive supply voltage

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