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M2V64S20DTP Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part No. M2V64S20DTP
Description  64M Synchronous DRAM
Download  51 Pages
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M2V64S20DTP Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor

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Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
1
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up
to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v±0.3V power supp ly
- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst typ e- sequential and interleave (programmable)
- Byte Control- DQM L and DQMU for M2V64S40DTP
- Random column access
- Auto p recharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
DESCRIPTION
FEATURES
PRELIMINARY
Some of contents are described for general products and are
subject to change w ithout notice.
ITEM
tCLK
M2V64S20/30/40DTP
-7
-8
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle T ime
(Min.)
Active to Precharge Command Period
(Min.)
Row to Column Delay
(Min.)
Access Time from CLK
(Max.) (CL=3)
Ref /Active Command Period
(Min.)
Operation Current
(Max.)
(Single Bank)
Self Refresh Current
(Max.)
10ns
50ns
20ns
6ns
70ns
1mA
10ns
50ns
20ns
6ns
70ns
1mA
V64S20D
V64S30D
V64S40D
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
1mA
70mA
70mA
80mA
70mA
70mA
80mA
75mA
75mA
85mA


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