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ST72334J Datasheet(PDF) 53 Page - STMicroelectronics

Part No. ST72334J
Description  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST72334J Datasheet(HTML) 53 Page - STMicroelectronics

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ST72334J/N, ST72314J/N, ST72124J
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6.4 16-BIT TIMER
6.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (
input capture) or generation of up to two out-
put waveforms (
output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
6.4.2 Main Features
s
Programmable prescaler: f
CPU divided by 2, 4 or 8.
s
Overflow status flag and maskable interrupt
s
External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
s
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
s
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
s
Pulse width modulation mode (PWM)
s
One pulse mode
s
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 35.
*Note: Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
6.4.3 Functional Description
6.4.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 14 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 internal
processorclock cycles depending on the CC1 and
CC0 bits.


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