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74LV377 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV377
Description  Octal D-type flip-flop with data enable; positive edge-trigger
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LV377 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
2
1998 Jun 10
853–1935 19545
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Ideal for addressable register applications
Data enable for address and data synchronization applications
Eight positive-edge triggered D-type flip-flops
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Qn) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CP to Qn
CL = 15pF
V
33V
13
ns
fmax
Maximum clock frequency
VCC = 3.3V
77
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per flip-flop
Notes 1 and 2
20
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2
fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°C to +125°C
74LV377 N
74LV377 N
SOT146-1
20-Pin Plastic SO
–40
°C to +125°C
74LV377 D
74LV377 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV377 DB
74LV377 DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV377 PW
74LV377PW DH
SOT360-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
E
Data enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0 to Q7
flip-flop outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data inputs
10
GND
Ground (0V)
11
CP
Clock input
(LOW-to-HIGH, edge-triggered)
20
VCC
Positive supply voltage
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
OPERATING MODES
CP
E
Dn
Qn
Load ‘‘1’’
l
h
H
Load ‘‘0’’
l
l
L
Hold (do nothing)
X
h
H
X
X
No change
No change
H
= HIGH voltage level
h
= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L
= LOW voltage level
l
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
= LOW–to–HIGH CP transition
X
= Don’t care


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