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74LV373 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV373
Description  Octal D-type transparent latch 3-State
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LV373 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
2
1998 Jun 10
853–1934 19545
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C
Common 3-State output enable input
Output capability: bus driver
I
CC category: MSI
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
Dn to Qn
LE to Qn
CL = 15pF
VCC = 3.3V
10
12
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per latch
Notes 1, 2
22
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi ) (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°C to +125°C
74LV373 N
74LV373 N
SOT146-1
20-Pin Plastic SO
–40
°C to +125°C
74LV373 D
74LV373 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV373 DB
74LV373 DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV373 PW
74LV373PW DH
SOT360-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0–Q7
3-State latch outputs
3, 4, 7, 8, 13,
14, 17, 18
D0–D7
Data inputs
10
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
VCC
Positive supply voltage


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