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74LV273 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV273
Description  Octal D-type flip-flop with reset; positive-edge trigger
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LV273 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
2
1998 May 29
853–1965 19466
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Ideal buffer for MOS microprocessor or memory
Common clock and master reset
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The 74LV273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CP to Qn;
MR to Qn
CL = 15pF
VCC = 3.3V
12
13
ns
fmax
Maximum clock frequency
110
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per flip-flop
Notes 1 and 2
20
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°C to +125°C
74LV273 N
74LV273 N
SOT146-1
20-Pin Plastic SO
–40
°C to +125°C
74LV273 D
74LV273 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV273 DB
74LV273 DB
SOT339-1
20-Pin Plastic TSSOP
–40
°C to +125°C
74LV273 PW
74LV273PW DH
SOT360-1


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