DAC124S085CIMM datasheet(15/18 Pages) NSC | 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output

Part #	DAC124S085CIMM

Description	12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output

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Manufacturer	NSC [National Semiconductor (TI)]

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1.0 Functional Description (Continued)

1.6 POWER-ON RESET

The power-on reset circuit controls the output voltages of the

four DACs during power-up. Upon application of power, the

DAC registers are filled with zeros and the output voltages

are 0V. The outputs remain at 0V until a valid write sequence

is made to the DAC.

1.7 POWER-DOWN MODES

The DAC124S085 has four power-down modes, two of

which are identical. In power-down mode, the supply current

drops to 20 µA at 3V and 30 µA at 5V. The DAC124S085 is

set in power-down mode by setting OP1 and OP0 to 11.

Since this mode powers down all four DACs, the address

bits, A1 and A0, are used to select different output termina-

tions for the DAC outputs. Setting A1 and A0 to 00 or 11

causes the outputs to be tri-stated (a high impedance state).

While setting A1 and A0 to 01 or 10 causes the outputs to be

terminated by 2.5 k

Ω or 100 kΩ to ground respectively (see

Table 1).

TABLE 1. Power-Down Modes

A1

A0

OP1

OP0

Operating Mode

0

1

High-Z outputs

0

1

2.5 k

Ω to GND

1

0

1

100 k

Ω to GND

1

High-Z outputs

The bias generator, output amplifiers, resistor strings, and

other linear circuitry are all shut down in any of the power-

down modes. However, the contents of the DAC registers

are unaffected when in power-down. Each DAC register

maintains its value prior to the ADC124S085 being powered

down unless it is changed during the write sequence which

instructed it to recover from power down. Minimum power

consumption is achieved in the power-down mode with

SYNC and D

IN idled low and SCLK disabled. The time to exit

power-down (Wake-Up Time) is typically 0.8 µsec at 3V and

0.5 µsec at 5V.

2.0 Applications Information

2.1 USING REFERENCES AS POWER SUPPLIES

While the simplicity of the DAC124S085 implies ease of use,

it is important to recognize that the path from the reference

input (V

REFIN) to the VOUTs will have essentially zero Power

Supply Rejection Ratio (PSRR). Therefore, it is necessary to

provide a noise-free supply voltage to V

REFIN. In order to

utilize the full dynamic range of the DAC124S085, the supply

pin (V

A) and VREFIN can be connected together and share

the same supply voltage. Since the DAC124S085 consumes

very little power, a reference source may be used as the

reference input and/or the supply voltage. The advantages of

using a reference source over a voltage regulator are accu-

racy and stability. Some low noise regulators can also be

used. Listed below are a few reference and power supply

options for the DAC124S085.

2.1.1 LM4130

The LM4130, with its 0.05% accuracy over temperature, is a

good choice as a reference source for the DAC124S085.

The 4.096V version is useful ifa0to 4.095V output range is

desirable or acceptable. Bypassing the LM4130 VIN pin with

a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor

will improve stability and reduce output noise. The LM4130

comes in a space-saving 5-pin SOT23.

2.1.2 LM4050

Available with accuracy of 0.44%, the LM4050 shunt refer-

ence is also a good choice as a reference for the

DAC124S085. It is available in 4.096V and 5V versions and

comes in a space-saving 3-pin SOT23.

The minimum resistor value in the circuit of Figure 6 must be

chosen such that the maximum current through the LM4050

does not exceed its 15 mA rating. The conditions for maxi-

mum current include the input voltage at its maximum, the

LM4050 voltage at its minimum, and the DAC124S085 draw-

ing zero current. The maximum resistor value must allow the

LM4050 to draw more than its minimum current for regula-

tion plus the maximum DAC124S085 current in full opera-

tion. The conditions for minimum current include the input

voltage at its minimum, the LM4050 voltage at its maximum,

the resistor value at its maximum due to tolerance, and the

DAC124S085 draws its maximum current. These conditions

can be summarized as

R(min)=(V

IN(max) − VZ(min) ) /IZ(max)

and

R(max)=(V

IN(min) − VZ(max))/((IDAC(max) + IZ(min) )

where V

Z(min) and VZ(max) are the nominal LM4050 output

voltages ± the LM4050 output tolerance over temperature,

I

Z(max)

is the maximum allowable current through the

20173213

FIGURE 5. The LM4130 as a power supply

20173214

FIGURE 6. The LM4050 as a power supply

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DAC124S085CIMM Datasheet(PDF) 15 Page - National Semiconductor (TI)

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