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DAC124S085CIMM Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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DAC124S085CIMM Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 18 page  1.0 Functional Description 1.1 DAC SECTION The DAC124S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at V REFIN and is shared by all four DACs. For simplicity, a single resistor string is shown in Figure 3. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of: V OUTA,B,C,D =VREFIN x (D / 4096) where D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any value between 0 and 4095. This configuration guarantees that the DAC is monotonic. 1.2 OUTPUT AMPLIFIERS The output amplifiers are rail-to-rail, providing an output voltage range of 0V to V A when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V A, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than V A, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in the Electrical Tables. The output amplifiers are capable of driving a load of 2 k Ω in parallel with 1500 pF to ground or to V A. The zero-code and full-scale outputs for given load currents are available in the Electrical Characterisics Table. 1.3 RERENCE VOLTAGE The DAC124S085 uses a single external reference that is shared by all four channels. The reference pin, V REFIN,isnot buffered and has an input impedance of 30 k Ω. It is recom- mended that V REFIN be driven by a voltage source with low output impedance. The reference voltage range is 1.0V to V A, providing the widest possible output dynamic range. 1.4 SERIAL INTERFACE The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Serial Timing Diagram, Figure 2). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel ad- dress, mode of operation and/or register contents) is ex- ecuted. At this point the SYNC line may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC. Since the SYNC and D IN buffers draw more current when they are high, they should be idled low between write se- quences to minimize power consumption. 1.5 INPUT SHIFT REGISTER The input shift register, Figure 4, has sixteen bits. The first two bits are address bits. They determine whether the reg- ister data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine the mode of operation (writing to a DAC register without updat- ing the outputs of all four DACs, writing to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0’s corresponding to an output of 0V and all 1’s corresponding to a full-scale output of V REFIN - 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2. Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. Under this condi- tion, the DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages. 20173207 FIGURE 3. DAC Resistor String 20173208 FIGURE 4. Input Register Contents www.national.com 14 |
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