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M36W0R5020T0 Datasheet(PDF) 6 Page - STMicroelectronics

Part No. M36W0R5020T0
Description  32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M36W0R5020T0 Datasheet(HTML) 6 Page - STMicroelectronics

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SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). Addresses
A0-A17
are common inputs for the Flash memory and
SRAM components. The other lines (A18-A20) are
inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the
internal state machine. The Flash memory is ac-
cessed through the Chip Enable signal (EF) and
through the Write Enable (WF) signal, while the
SRAM is accessed through two Chip Enable sig-
nals (E1S and E2S) and the Write Enable signal
(WS).
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Write Bus op-
eration.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is Low, VIL, and Reset is High, VIH,
the device is in active mode. When Chip Enable is
at VIH the Flash memory is deselected, the outputs
are high impedance and the power consumption is
reduced to the standby level.
It is not allowed to set EF at VIL, E1S at VIL and E2S
at VIH at the same time.
Flash Output Enable (GF). The Output Enable
pin controls data outputs during Flash memory
Bus Read operations.
Flash Write Enable (WF). The Write Enable in-
put controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR032FT/B datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 7., Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash memory
output signal used during Synchronous Read to in-
dicate whether the data on the output bus are val-
id. This output is high impedance when the Flash
memory Chip Enable is at VIH or Reset is at VIL. It
can be configured to be active during the wait cy-
cle or one clock cycle in advance. The WAITF sig-
nal is not gated by Output Enable.
SRAM Chip Enable inputs (E1S, E2S). The
Chip Enable inputs activate the SRAM memory
control logic, input buffers and decoders. E1S at
VIH with E2S at VIH deselects the memory, reduc-
ing the power consumption to the standby level,
whereas E2S at VIL deselects the memory and re-
duces the power consumption to the Power-down
level, regardless of the level of E1S. E1S and E2S
can also be used to control writing to the SRAM
memory array, while WS remains at VIL. It is not al-
lowed to set EF at VIL, E1S at VIL and E2S at VIH at
the same time.
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a Read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The
Upper
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UBS is active low.


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