PRELIMINARY
CY7C1353G
Document #: 38-05515 Rev. *A
Page 9 of 13
tCLZ
Clock to Low-Z[14, 15, 16]
0
0
0
ns
tCHZ
Clock to High-Z[14, 15, 16]
3.5
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
3.5
ns
tOELZ
OE LOW to Output Low-Z[14, 15, 16]
0
0
0
ns
tOEHZ
OE HIGH to Output High-Z[14, 15, 16]
3.5
3.5
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
2.0
2.0
ns
tALS
ADV/LD Set-up Before CLK Rise
1.5
2.0
2.0
ns
tWES
WE, BWX Set-Up Before CLK Rise
1.5
2.0
2.0
ns
tCENS
CEN Set-up Before CLK Rise
1.5
2.0
2.0
ns
tDS
Data Input Set-up Before CLK Rise
1.5
2.0
2.0
ns
tCES
Chip Enable Set-up Before CLK Rise
1.5
2.0
2.0
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
ns
Switching Characteristics Over the Operating Range (continued)[17, 18]
Parameter
Description
133 MHz
117 MHz
100 MHz
Unit
Min.
Max.
Min.
Max.
Min.
Max.
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