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CY7C1305AV25-100 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1305AV25-100
Description  18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1305AV25-100 Datasheet(HTML) 9 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1305AV25
CY7C1307AV25
Document #: 38-05496 Rev. *A
Page 9 of 21
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Applied to Outputs in High-Z State –0.5V to VDDQ + 0.5V
DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD[12]
VDDQ[12]
Com’l
0°C to +70°C
2.5 ± 0.1V
1.4V to 1.9V
Electrical Characteristics Over the Operating Range[13]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VOH
Output HIGH Voltage
Note 14
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 15
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW) Output HIGH Voltage
IOH = –0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOH = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage[11]
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage[11, 16]
–0.3
VREF – 0.1
V
VIN
Clock Input Voltage
–0.3
VDDQ + 0.3
V
IX
Input Load Current
GND
≤ VI ≤ VDDQ
–5
5
µA
IOZ
Output Leakage Current
GND
≤ VI ≤ VDDQ, Output Disabled
–5
5
µA
VREF
Input Reference Voltage[17] Typical value = 0.75V
0.68
0.75
0.95
V
IDD
VDD Operating Supply
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
167 MHz
650
mA
133 MHz
620
mA
100 MHz
590
mA
ISB1
Automatic
Power-Down
Current
Max. VDD, Both Ports
Deselected,
VIN ≤ VIH or VIN < VIL
f = fMAX = 1/tCYC, Inputs Static
167 MHz
420
mA
133 MHz
400
mA
100 MHz
380
mA
AC Input Requirements Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VIH
Input High (Logic 1) Voltage
VREF + 0.2
V
VIL
Input Low (Logic 0) Voltage
VREF – 0.2
V
Thermal Resistance[18]
Parameter
Description
Test Conditions
165 FBGA
Package
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, per
EIA/JESD51.
16.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.5
°C/W
Notes:
11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
12. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
13. All Voltage referenced to Ground.
14. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175<= RQ <= 350.
15. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175<= RQ <= 350.
16. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
17. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.


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