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CY7C1347D
Document #: 38-05022 Rev. *D
Page 11 of 21
TAP Timing and Test Conditions
Identification Register Definitions
Instruction Field
128K x 36
Description
Revision Number (31:28)
XXXX
Reserved for revision number.
Device Depth (27:23)
00111
Defines depth of words.
Device Width (22:18)
00011
Defines width of bits.
Reserved (17:12)
XXXXXX
Reserved for future use.
Cypress Jedec Id Code (11:1)
00011100100
Allows unique identification of DEVICE vendor.
ID Register Presence Indicator (0)
1
Indicates the presence of an ID register.
(a)
3.3V / 2.5V
VSS
ALL INPUT PULSES
1.5V
1.5 ns
1.5 ns
Vt = 1.5V
TDO
Z
0 = 50 Ω
50
Ω
20 pF
for 3.3V VCCQ or
VCCQ/2 for 2.5V VCCQ
TEST CLOCK
(TCK)
tTHTH
tTHTL
tTLTH
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
TEST DATA OUT
(TDO)
tMVTH tTHMX
tDVTH
tTHDX
tTLQX
tTLQV
Scan Register Sizes
Register Name
Bit Size (x36)
Instruction
3
Bypass
1
ID
32
Boundary Scan
51