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CY7C1347D
Document #: 38-05022 Rev. *D
Page 9 of 21
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
x
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TDI
TDI
[9]
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
Min.
Max.
Unit
VIH
Input High (Logic 1)
Voltage: Inputs[10, 11]
VCCQ = 3.3 V
2.0
4.6
V
VCCQ = 2.5V
1.7
4.6
V
Input High (Logic 1)
Voltage: Data[10, 11]
VCCQ = 3.3 V
2.0
VCCQ + 0.3
V
VCCQ = 2.5V
1.7
VCCQ + 0.3
VIL
Input Low (Logic 0) Voltage: Inputs and
Data[10, 11]
VCCQ = 3.3 V
–0.5
0.8
V
VCCQ = 2.5V
–0.3
0.7
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current 0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[10, 12]
IOLC = 100 µA0.2
V
VOHC
LVCMOS Output High Voltage[10, 12]
IOHC = 100 µAVCCQ – 0.2
V
Notes:
9. X = 69.
10. All Voltage referenced to VSS (GND).
11. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed 3.6V. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
12. This parameter is sampled.
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