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COMMERCIALTEMPERATURERANGE

IDT72V70810 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 1,024 x 1,024

used to designate the connection memory or the data Memory. The stream

addressbitsselectinternalmemorysubsectionscorrespondingtoinputoroutput

serialstreams.

The data in the IMS register consists of block programming bits (BPD0-

BPD4),blockprogrammingenablebit(BPE),outputstandbybit(OSB)andstart

frameevaluationbit(SFE).Theblockprogrammingandtheblockprogramming

enablebitsallowsuserstoprogramtheentireconnectionmemory(seeMemory

BlockProgrammingsection).IftheODEpinislow,theOSBbitenables(ifhigh)

of the OSB bit is ignored and all TX output drivers are enabled.

CONNECTION MEMORY CONTROL

TheCCOpinisa16.384Mb/soutput,whichcarries2,048bits.Thecontents

of the CCO bit of each connection memory location are output on the CCO pin

once every frame. The contents of the CCO bits of the connection memory are

transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection

memory) and are synchronous with the data rates on the other serial streams.

The CCO bit is output one channel before the corresponding channel on the

serialstreams.

If the ODE pin or the OSB bit is high, the OE bit of each connection memory

location controls the output drivers-enables (if high) or disables (if low). See

Table 4 for detail.

Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween

Processor Mode and Connection Mode. If high, the contents of the connection

memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and

the channel address bit (CAB) of the connection memory defines the source

information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput

from data memory.

The

V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation

allows the per-channel selection between variable and constant throughput

delay modes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., RX n channel m data comes from the

TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For

proper per-channel loopback operation, the contents of the frame delay offset

registers must be set to zero.

INITIALIZATION OF THE IDT72V70810

After power up, the state of the connection memory is unknown. As such,

theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe

ODE is low, the microprocessor can initialize the device, program the active

paths, and disable unused outputs by programming the OE bit in connection

memory. Once the device is configured, the ODE pin (or OSB bit depending

on initialization) can be switched.