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IDT72V70810 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V70810
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70810 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
clock(CLK)periodsforwardwithresolutionof½clockperiod.Theoutputframe
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70810 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurementcyclestarted.
In ST-BUS® mode, the falling edge of the frame measurement signal (FE)
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 7 & Figure 4 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
TheIDT72V70810providesuserswiththecapabilityofinitializingtheentire
connectionmemoryblockintwoframes.Tosetbits11to15ofeveryconnection
memorylocation,firstprogramthedesiredpatterninbits5to9oftheIMSregister.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT72V70810
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesontheper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C bit of the connection memory.
VARIABLE DELAY MODE (
V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70810 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifinput
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 1 shows the possible delays for the IDT72V70810 in the
variable delay mode.
CONSTANT DELAY MODE (
V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70810, the minimum throughput delay achievable in the constant
delaymodewillbeoneframe. SeeTable2forpossibledelaysinconstantdelay
mode.
MICROPROCESSOR INTERFACE
The IDT72V70810 provides a parallel microprocessor interface for multi-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected to
the device. If the IM pin is high, the device monitors the AS/ALE and DS/
RD to
determine what mode the IDT72V70810 should operate in.
If DS/
RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/
RDishighattherisingedgeofAS/ALE,thenthemode
2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/
RD),Read/Write/Write(R/W/WR),
Chip select (
CS) and Data transfer acknowledge (DTA). See Figure 12 and
Figure 13 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(
CS, DS, R/W andDTA). See Figure 14 and 15 for Motorola non-multiplexed
microporttiming.
The IDT72V70810 microport provides access to the internal registers,
connectionanddatamemories.Alllocationsprovideread/writeaccessexcept
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70810.
If the A7 address input is low, then A6 through A0 are used to address the
interfacemodeselection(IMS),control(CR),framealignment(FAR)andframe
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
used to select 128 locations corresponding to data rate of the ST-BUS®. The
addressinputlinesandthestreamaddressbits(STA)ofthecontrolregisterallow
access to the entire data and connection memories. The control and IMS
registers together control all the major functions of the device, see Figure 3.
As explained in the Serial Data Interface Timing and Switching Configura-
tionssections,aftersystempower-up,theIMSregistershouldbeprogrammed
immediatelytoestablishthedesiredswitchingconfiguration.
The data in the control register consists of the memory block programming
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is


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