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IDT72V70810 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT72V70810
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70810 Datasheet(HTML) 4 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
FUNCTIONAL DESCRIPTION
The IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 Kbit/s
PCMorNx64Kbit/schanneldata.Thedevicemaintainsframeintegrityindata
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70810 have a bit rate of 8.192 Mb/s
andarearrangedin125mswideframes,whichcontain128channels.Thedata
rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slotsonaperchannelbasisallowingfortransferofcontrolandstatusinformation.
The IDT72V70810 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS® or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70810 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfacesprovidecompatibilitywithmultiplexedandMotorolanon-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
of glue logic necessary to convert the signals (R/
W/WR, DS/RD, AS/ALE).
Theframeoffsetcalibrationfunctionallowsuserstomeasuretheframeoffset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70810 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8 KHz
input frame pulse (
F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 1,024 bytes.
Data to be output on the serial streams (TX0-7) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
tobeoutputfromconnectionmemory,theconnectionmemorycontrolbitsmust
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
IntheConnectionMode,theaddressesoftheinputsourcedataforalloutput
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
theoutputstreams.Fordetailsontheuseofthesourceaddressdata(CABand
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferredtotheparallel-to-serialconvertersandthenontoaTXoutputstream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
outputstreamandchannelnumberandistransferreddirectlytotheparallel-to-
serial converter one time-slot before it is to be output. This data will be output
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
AstheIDT72V70810canbeusedinawidevarietyofapplications,thedevice
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70810 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function.Inaddition,oneofthesebitsallowstheusertocontroltheCCOoutput.
Ifanoutputchannelissettoahigh-impedancestatethroughtheconnection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS®
outputscanbeplacedinahighimpedancestatebyeitherpullingtheODEinput
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connectionmemorybits.
The connection memory data can be accessed via the microprocessor
interface.Theaddressingofthedevicesinternalregisters,dataandconnection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
dataratesof8.192Mb/s,themasterclock(CLK)mustbe16.384MHz.Theinput
and output stream data rates will always be identical.
TheIDT72V70810providestwodifferentinterfacetimingmodesST-BUS®/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70810
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS®/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS®orGCIformat.TheIDT72V70810automaticallydetectsthepresence
of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS®
format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse
isinST-BUS®format.ThetimingrelationshipbetweenCLK,HCLKandtheframe
pulse is shown in Figure 9.
WhenWFPSpinishigh,theframealignmentevaluationfeatureisdisabled.
However,theframeinputoffsetregistersmaystillbeprogrammedtocompensate
for the varying frame delays on the serial input streams.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
dataisoftendelayed,thisfeatureisusefulincompensatingfortheskewbetween
clocks.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR).Themaximumallowableskewis+4.5master


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