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L6926D1 Datasheet(PDF) 4 Page - STMicroelectronics

Part # L6926D1
Description  HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6926D1 Datasheet(HTML) 4 Page - STMicroelectronics

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L6926
4/11
(*) Guaranteed by design
4
OPERATION DESCRIPTION
The main loop uses slope compensated PWM current mode architecture. Each cycle the high side MOSFET
is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current)
increases. When this current reaches the threshold (set by the output of the error amplifier E/A), the peak current
limit comparator PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock
cycle begins or the current flowing through it goes down to zero (ZERO CROSSING comparator). The peak in-
ductor current required to trigger PEAK_CL depends on the slope compensation signal and on the output of the
error amplifier.
In particular, the error amplifier output depends on the VFB pin voltage. When the output current increases, the
output capacitor is discharged and so the VFB pin decreases. This produces increase of the error amplifier out-
put, so allowing a higher value for the peak inductor current. For the same reason, when due to a load transient
the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet
the new load requirements.
The slope compensation signal allows the loop stability also in high duty cycle conditions (see related section)
Figure 4. Device Block Diagram
4.1 Modes of Operation
Depending on the SYNC pin value the device can operate in low consumption or low noise mode. If the SYNC
pin is high (higher than 1.3V) the low consumption mode is selected while the low noise mode is selected if the
SYNC pin is low (lower than 0.5V).
4.1.1 Low Consumption Mode
VPGOOD
Power Good Threshold
VOUT = Vfb
90
%Vout
∆VPGOOD
Power Good Hysteresis
VOUT = Vfb
4
%Vout
VPgood(low)
Power Good Low Voltage
Run to GND
0.4
V
ILK-PGOOD
Power Good Leakage Current
(*)
VPGOOD = 3.6V
50
nA
PROTECTIONS
HOVP
Hard overvoltage threshold
VOUT = Vfb
10
%Vout
VCC
SYNC
COMP
PGOOD
GND
DRIVER
GND
GND
GND
PEAK
CL
VALLEY
CL
Vcc
ZERO
CROSSING
LOOP
CONTROL
OSCILLATOR
LOW
NOISE/
CONSUMPTION
LX
OVP
VREF
FB
E/A
P
GOOD
POWER
PMOS
POWER
NMOS
SENSE
PMOS
SENSE
NMOS
Vcc
0.6V
VREF
0.9V
SLOPE
RUN
VCC
SYNC
COMP
PGOOD
GND
DRIVER
GND
GND
GND
PEAK
CL
VALLEY
CL
Vcc
ZERO
CROSSING
LOOP
CONTROL
OSCILLATOR
LOW
NOISE/
CONSUMPTION
LX
OVP
VREF
FB
E/A
P
GOOD
POWER
PMOS
POWER
NMOS
SENSE
PMOS
SENSE
NMOS
Vcc
0.6V
VREF
0.9V
SLOPE
RUN


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