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PTMA403033P1AD Datasheet(PDF) 3 Page - Texas Instruments |
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PTMA403033P1AD Datasheet(HTML) 3 Page - Texas Instruments |
3 / 33 page www.ti.com PTMA403033 ELECTRICAL CHARACTERISTICS PTMA403033 PTMA402050 PTMA401120 SLTS259A – FEBRUARY 2006 – REVISED MARCH 2006 T A = 25°C, VI = 48 V, VO = 3.3 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated) PTMA403033 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX PO Output power Over VI range 10 W IO Output current Over VI range 0.1 (1) 3 (2) A ILIM Current Limit Threshold Shutdown, followed by autorecovery 4.25 A VI Input voltage range Over IO range 36 48 75 V Set-point voltage tolerance ±2 (3) %VO Temperature variation -40°C ≤ T A ≤ 85°C ±1 %VO Line regulation Over VI range ±3 mV VO Load regulation Over IO range ±10 mV Total output voltage variation Includes set-point, line, load, –40°C ≤ T A ≤ 85°C 3 5 (3) %VO Trim adjust range Over VI range 3.0 3.6 V η Efficiency PO = POmax 82% VO Ripple (peak-to-peak) 20-MHz bandwidth 65 mVpp 0.1 A/µs load step, Recovery time 750 µs Transient response 50% to 100% VO over/undershoot ±150 mV IOmax Referenced to VI– Input high voltage (VIH) 4.5 Open (4) V Output enable input (pin 3) Input low voltage (VIL) –0.2 0.8 Input low current (IIL) 1 mA Standby input current Pin 3 open 8 mA UVLO Undervoltage lockout 32 34 V OVP Output Overvoltage Protection 3.7 5.4 V ƒ S Switching frequency Over VI and IO ranges (non-Sync option) 250 300 350 kHz Free-running 180 215 (5) 250 Sync switching frequency kHz Synchronization range 250 (5) 350 (5) SYNC high-level input voltage 3.5 6 V low-level input voltage –0.3 0.5 V clock duty cycle 25 75 % CI External input capacitance 0 47 µF CO External output capacitance 0 47 (6) 1000 µF VISO Isolation voltage 1,500 Vdc CISO Isolation capacitance Primary-Secondary 1,100 pF RISO Isolation resistance 10 M Ω (1) The converter requires a minimum load current for proper operation. However, the converter is not damaged when operated under a no-load condition. (2) See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures. (3) The set-point voltage tolerance is affected by the tolerance and stability of RTRIM. The stated limit is unconditionally met if RTRIM has a tolerance of ≤1%, with ≤100 ppm/°C temperature stability. (4) The Enable input (pin 3) has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently connected to VI– (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is typically less than 5 V. See the Application Information for a more detailed description. (5) A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz maximum. (6) An output capacitor is not required for proper operation. However, additional capacitance at the load improves the transient response. 3 Submit Documentation Feedback |
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