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74LV125DB Datasheet(PDF) 6 Page - NXP Semiconductors |
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74LV125DB Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74LV125 Quad buffer/line driver (3-State) 1998 Apr 28 6 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V; VX = VOL + 0.1 × VCC at VCC < 2.7 V and ≥ 4.5 V. VY = VOH – 0.3 V at VCC ≥ 2.7 V and ≤ 3.6 V; VY = VOH – 0.1 ⋅ VCC at VCC < 2.7 V and ≥ 4.5 V. SV00459 VM nA INPUT nY OUTPUT VM tPLH t PHL GND Vl V OL V OH Figure 1. Input (nA) to output (nY) propagation delays and output transition times. SV00458 outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ VX VY VM VM nOE Input VI GND VCC VOL VOH GND OUTPUT HIGH-to-OFF OFF-to-HIGH OUTPUT LOW-to-OFF OFF-to-LOW VM Figure 2. 3-state enable and disable times. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL RL = 1k VCC Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 2.7V 2.7–3.6V w 4.5V VCC 50 pF SV00896 S1 tPLZ/tPZL tPHZ/tPZH Open 2 * VCC GND RL = 1k Open 2 * VCC GND RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. Figure 3. Load circuitry for switching times. |
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