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74LV125 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV125
Description  Quad buffer/line driver 3-State
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LV125 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LV125
Quad buffer/line driver (3-State)
2
1998 Apr 28
853–1901 19290
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C.
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C.
Output capability: bus driver
I
CC category: MSI
DESCRIPTION
The 74LV125 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT125.
The 74LV125 consists of four non-inverting buffers/line drivers with
3-state outputs. The 3-state outputs (nY) are controlled by the output
enable input (nOE). A HIGH at nOE causes the outputs to assume a
high impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nA to nY
CL = 15 pF;
VCC = 3.3 V
9
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per buffer
VCC = 3.3 V;
VI = GND to VCC1
22
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°C to +125°C
74LV125 N
74LV125 N
SOT27-1
14-Pin Plastic SO
–40
°C to +125°C
74LV125 D
74LV125 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV125 DB
74LV125 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV125 PW
74LV125PW DH
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 4, 10, 13
1OE – 4OE
Data enable inputs (active LOW)
2, 5, 9, 12
1A – 4A
Data inputs
3, 6, 8, 11
1Y – 4Y
Data Outputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUT
nOE
nA
nY
L
L
L
L
H
H
H
X
Z
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state


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