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M25PE80 Datasheet(PDF) 6 Page - STMicroelectronics

Part No. M25PE80
Description  8 Mbit, low-voltage, Page-Erasable Serial Flash memory with Byte alterability, 50MHz SPI bus, standard pinout
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M25PE80 Datasheet(HTML) 6 Page - STMicroelectronics

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Description
M25PE80
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1
Description
The M25PE80 is an 8 Mbit (1 Mb × 8) Serial Paged Flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 Bytes at a time, using the Page Write
or Page Program instruction. The Page Write instruction consists of an integrated Page
Erase cycle followed by a Page Program cycle.
The memory is organized as 16 sectors that are further divided up into 16 subsectors each
(256 subsectors in total). Each sector contains 256 pages and each subsector contains 16
pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting
of 4096 pages, or 1 048 576 bytes
The memory can be erased a page at a time, using the Page Erase instruction, a subsector
at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase
instruction, or as a whole, using the Bulk Erase instruction.
The memory can be Write Protected by either Hardware or Software using a mix of volatile
and non-volatile protection features, depending on the application needs. The protection
granularity is of 64 Kbytes (sector granularity).
In order to meet environmental requirements, ST offers the M25PE80 in ECOPACK®
packages. ECOPACK® packages are Lead-Free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Important note
This datasheet details the functionality of the M25PE80 devices, based on the previous T7Y
process or based on the current T9HX process. Delivery of parts in T9HX process starts
from June 2007.
What are the changes?
The M25PE80 in T9HX process offers the following additional features:
the whole memory array is partitioned into 4-Kbyte subsectors
two new instructions: Write Status Register (WRSR) and 4-Kbyte SubSector Erase
(SSE)
Status Register: 4 bits can be written (BP0, BP1, BP2, SRWD)
WP input (pin 3): Write protection limits are extended, depending on the value of the
BP0, BP1, BP2, SRWD bits. The WP Write protection remains the same if bits (BP2,
BP1, BP0) are set to (0, 0, 1).
smaller die size allowing assembly into an SO8N package
Suppressed feature:
The Write protection (defined by the WL and LD lock bits) of the 4-Kbyte SubSectors in
the top and bottom sectors is no longer offered.
For more details please refer to PCNMPG062148.


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