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74HCT7273 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74HCT7273
Description  Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HCT7273 Datasheet(HTML) 2 Page - NXP Semiconductors

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1999 Oct 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
• Ideal buffer for MOS
microprocessor or memory
• Eight positive edge-triggered
D-type flip-flops
• Common clock and master reset
• Output capability: standard (open
drain)
• ICC category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop.
A LOW level on the MR input forces all outputs LOW, independently of the clock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
between GND and VOmax. This allows the device to be used as a LOW-to-HIGH
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf = 6.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo)+ ∑(V02/RL) × duty factor LOW where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
RL = pull-up resistor in MΩ;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC − 1.5 V.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPZL/tPLZ
propagation delay
CL = 50 pF; VCC = 4.5 V
CP to Qn
16
ns
MR to Qn
23
ns
fmax
maximum clock frequency
56
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 1 MHz; notes 1 and 2
37
pF


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