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7403 Datasheet(PDF) 27 Page - NXP Semiconductors |
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7403 Datasheet(HTML) 27 Page - NXP Semiconductors |
27 / 28 page September 1993 27 Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Note to Fig.23 Sequence 1 (both FIFOS empty, starting SHIFT-IN process) After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4). Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18). handbook, full pagewidth DORB OUTPUT DIRB OUTPUT DORA OUTPUT DIRA OUTPUT Q OUTPUT nB QnA OUTPUT SI INPUT A D INPUT nA MR INPUT SO INPUT B sequence 1 sequence 2 sequence 3 sequence 4 sequence 5 sequence 6 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) MGA687 |
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