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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet

Rev. 03 — 12 November 2004

4 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

6.

Pinning information

6.1 Pinning

6.2 Pin description

Fig 4.

Logic diagram (one flip-flop)

001aab982

C

C

K

J

R

CP

C

C

C

C

C

C

C

C

Q

Q

Fig 5.

Pin configuration

73

1CP

1J

1R

1Q

1K

1Q

GND

2CP

2K

2R

2Q

2J

2Q

001aab978

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Table 3:

Pin description

Symbol

Pin

Description

1CP

1

clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered)

1R

2

asynchronous reset input for flip-flop 1 (active LOW)

1K

3

synchronous K input for flip-flop 1

4

positive supply voltage

2CP

5

clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered)

2R

6

asynchronous reset input for flip-flop 2 (active LOW)

2J

7

synchronous J input for flip-flop 2

2Q

8

complement flip-flop 2 output

2Q

9

true flip-flop 2 output

2K

10

synchronous K input for flip-flop 2