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74HC595BQ Datasheet(PDF) 14 Page - NXP Semiconductors |
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74HC595BQ Datasheet(HTML) 14 Page - NXP Semiconductors |
14 / 28 page 2003 Jun 25 14 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 trem removal time MR to SH_CP see Fig.10 2.0 +50 −19 − ns 4.5 +10 −7 − ns 6.0 +9 −6 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 9 30 − MHz 4.5 30 91 − MHz 6.0 35 108 − MHz Tamb = −40 to +85 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 −− 200 ns 4.5 −− 40 ns 6.0 −− 34 ns propagation delay ST_CP to An see Fig.8 2.0 −− 220 ns 4.5 −− 44 ns 6.0 −− 37 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 −− 220 ns 4.5 −− 44 ns 6.0 −− 37 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 −− 190 ns 4.5 −− 38 ns 6.0 −− 33 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 −− 190 ns 4.5 −− 38 ns 6.0 −− 33 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns storage clock pulse width HIGH or LOW see Fig.8 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns master reset pulse width LOW see Fig.10 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns tsu set-up time DS to SH_CP see Fig.9 2.0 65 −− ns 4.5 13 −− ns 6.0 11 −− ns set-up time SH_CP to ST_CP see Fig.8 2.0 95 −− ns 4.5 19 −− ns 6.0 16 −− ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) |
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