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74HC595N Datasheet(PDF) 17 Page - NXP Semiconductors |
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74HC595N Datasheet(HTML) 17 Page - NXP Semiconductors |
17 / 28 page 2003 Jun 25 17 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 Family 74HCT GND = 0 V; tr =tf = 6 ns; CL =50pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb =25 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 − 25 42 ns propagation delay ST_CP to Qn see Fig.8 4.5 − 24 40 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 − 23 40 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 − 21 35 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 − 18 30 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 16 6 − ns storage clock pulse width HIGH or LOW see Fig.8 4.5 16 5 − ns master reset pulse width LOW see Fig.10 4.5 20 8 − ns tsu set-up time DS to SH_CP see Fig.9 4.5 16 5 − ns set-up time SH_CP to ST_CP see Fig.8 4.5 16 8 − ns th hold time DS to SH_CP see Fig.9 4.5 +3 −2 − ns trem removal time MR to SH_CP see Fig.10 4.5 +10 −7 − ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 30 52 − MHz Tamb = −40 to +85 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 −− 53 ns propagation delay ST_CP to Qn see Fig.8 4.5 −− 50 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 −− 50 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 −− 44 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 −− 38 ns |
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