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74HC595N Datasheet(PDF) 15 Page - NXP Semiconductors |
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74HC595N Datasheet(HTML) 15 Page - NXP Semiconductors |
15 / 28 page 2003 Jun 25 15 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 th hold time DS to SH_CP see Fig.9 2.0 3 −− ns 4.5 3 −− ns 6.0 3 −− ns trem removal time MR to SH_CP see Fig.10 2.0 65 −− ns 4.5 13 −− ns 6.0 11 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.8 −− MHz 4.5 24 −− MHz 6.0 28 −− MHz Tamb = −40 to +125 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 −− 240 ns 4.5 −− 48 ns 6.0 −− 41 ns propagation delay ST_CP to Qn see Fig.8 2.0 −− 265 ns 4.5 −− 53 ns 6.0 −− 45 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 −− 265 ns 4.5 −− 53 ns 6.0 −− 45 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 −− 225 ns 4.5 −− 45 ns 6.0 −− 38 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 −− 225 ns 4.5 −− 45 ns 6.0 −− 38 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns storage clock pulse width HIGH or LOW see Fig.8 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns master reset pulse width LOW see Fig.10 2.0 110 −− ns 4.5 22 −− ns 6.0 19 −− ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) |
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