Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

74HC564 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. 74HC564
Description  Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Download  7 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC564 Datasheet(HTML) 6 Page - NXP Semiconductors

  74HC564 Datasheet HTML 1Page - NXP Semiconductors 74HC564 Datasheet HTML 2Page - NXP Semiconductors 74HC564 Datasheet HTML 3Page - NXP Semiconductors 74HC564 Datasheet HTML 4Page - NXP Semiconductors 74HC564 Datasheet HTML 5Page - NXP Semiconductors 74HC564 Datasheet HTML 6Page - NXP Semiconductors 74HC564 Datasheet HTML 7Page - NXP Semiconductors  
Zoom Inzoom in Zoom Outzoom out
 6 / 7 page
background image
December 1990
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
∆ICC) for a unit load of 1 is given in the family specifications.
To determine
∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
OE
D0 to D7
CP
0.80
0.25
1.00
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
−40 to +85 −40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
19
35
44
53
ns
4.5
Fig.6
tPZH/ tPZL
3-state output enable
time OE to Qn
19
35
44
53
ns
4.5
Fig.8
tPHZ/ tPLZ
3-state output disable
time OE to Qn
19
30
38
45
ns
4.5
Fig.8
tTHL/ tTLH
output transition time
5
12
15
18
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
18
8
23
27
ns
4.5
Fig.6
tsu
set-up time
Dn to CP
12
3
15
18
ns
4.5
Fig.7
th
hold time
Dn to CP
3
−2
3
3
ns
4.5
Fig.7
fmax
maximum clock pulse
frequency
27
56
22
18
MHz
4.5
Fig.6


Html Pages

1  2  3  4  5  6  7 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn