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74HC4520 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74HC4520
Description  Dual 4-bit synchronous binary counter
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74HC4520 Datasheet(HTML) 2 Page - NXP Semiconductors

   
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December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
74HC/HCT4520
FEATURES
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4520 are high-speed Si-gate CMOS
devices and are pin compatible with the “4520” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4520 are dual 4-bit internally synchronous
binary counters with an active HIGH clock input (nCP0)
and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3 = LOW)
independent of nCP0 and nCP1.
APPLICATIONS
• Multistage synchronous counting
• Multistage asynchronous counting
• Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay nCP0, nCP1 to nQn
CL = 15 pF; VCC = 5 V 2424ns
tPHL
propagation delay nMR to nQn
13
13
ns
fmax
maximum clock frequency
68
64
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per counter
notes 1 and 2
29
24
pF


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