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ZL50021 Datasheet(PDF) 49 Page - Zarlink Semiconductor Inc |
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ZL50021 Datasheet(HTML) 49 Page - Zarlink Semiconductor Inc |
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49 / 136 page  ZL50021 Data Sheet 49 Zarlink Semiconductor Inc. 17.2 Device Initialization on Reset Upon power up, the should be initialized as follows: • Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high • Set the TRST pin to low to disable the JTAG TAP controller • Reset the device by pulsing the RESET pin to zero for longer than 1 µs • After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the device to stabilize from the power down state before the first microprocessor port access can occur • Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs • Wait at least 500 µs prior to the next microport access (see Note below) • Use the block programming mode to initialize the connection memory • Release the ODE pin from low to high after the connection memory is programmed NOTE: If an external oscillator is used, the waiting time is 500 µs. Without the external oscillator, if CKi is 16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1ms; if CKi is 4.096 MHz, the waiting time is 2 ms. 17.3 Software Reset In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while SRSTSW (bit 1) resets the rest of the switch. 18.0 Pseudorandom Bit Generation and Error Detection The ZL50021 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudorandom code (ITU O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled. (This is the default state.) Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how many BER channels are to be monitored by the BER receiver. For each input stream, there is a set of registers for the BER test. The registers are as follows: • BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register (BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver. • BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the BER sequence will start to be compared. • BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256 channels at the data rates of 2.048, 4.096, 8.192 or 16.384 Mbps, respectively. The minimum length of the BER test is a single channel. The user must take care to program the correct channel length for the BER test so that the channel length does not exceed the total number of channels available in the stream. |
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Similar Description - ZL50021 |
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