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IDT72V3624L15 Datasheet(PDF) 32 Page - Integrated Device Technology |
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IDT72V3624L15 Datasheet(HTML) 32 Page - Integrated Device Technology |
32 / 34 page 32 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes) NOTE: 1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data (A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’t care inputs). In this second case, A0-A8 will have valid data (A9-A35 will be indeterminate). 4664 drw30 CLKB ENB B0-B35 MBB CSB W/RB CLKA MBF2 CSA MBA ENA A0-A35 W/ RA W1 tENH tDH tPMF tPMF tENH tDIS tEN tMDV tPMR FIFO2 Output Register W1 (Remains valid in Mail 2 Register after read) tENH tENH tENH tDS tENS1 tENS2 tENS2 tENS2 tENS2 |
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