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IDT72V3624 Datasheet(PDF) 12 Page - Integrated Device Technology |
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IDT72V3624 Datasheet(HTML) 12 Page - Integrated Device Technology |
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12 / 34 page  12 COMMERCIALTEMPERATURERANGE IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 TABLE 3 PORT B ENABLE .UNCTION TABLE LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs byaLOW-to-HIGHtransitionofCLKBwhen CSBisLOW,W/RBisHIGH,ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation. ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. Instead, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. Write and read timing diagrams for Port A can be found in Figure 7 and 14. Relevant Port B write and read cycle timing diagrams together with Bus-Matching and Endian select operations can be found in Figures 8 through 13. CSA W/ RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X High-Impedance None L H L X X Input None LH H L ↑ Input FIFO1 write LH H H ↑ Input Mail1 write L L L L X Output None LL H L ↑ Output FIFO2 read L L L H X Output None LL H H ↑ Output Mail2 read (set MBF2 HIGH) TABLE 2 PORT A ENABLE .UNCTION TABLE CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Function H X X X X High-Impedance None L L L X X Input None LL H L ↑ Input FIFO2 write LL H H ↑ Input Mail2 write L H L L X Output None LHH L ↑ Output FIFO1 read L H L H X Output None LHH H ↑ Output Mail1 read (set MBF1 HIGH) SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages.Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability of metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY/OUTPUT READY FLAGS ( EFA/ORA, EFB/ORB) These are dual purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output-Ready flag is HIGH, new dataispresentintheFIFOoutputregister.WhentheOutputReadyflagisLOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. |
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