Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

IDT72V3624 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V3624
Description  3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Download  34 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo 

IDT72V3624 Datasheet(HTML) 1 Page - Integrated Device Technology

 
Zoom Inzoom in Zoom Outzoom out
 1 / 34 page
background image
2001 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
DSC-4664/3
AUGUST 2001
3.3 VOLT CMOS SyncBiFIFOTM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3624
IDT72V3634
IDT72V3644
1
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
.UNCTIONAL BLOCK DIAGRAM
.EATURES:
••••• Memory storage capacity:
IDT72V3624–256 x 36 x 2
IDT72V3634–512 x 36 x 2
IDT72V3644–1,024 x 36 x 2
••••• Clock frequencies up to 100 MHz (6.5ns access time)
••••• Two independent clocked FIFOs buffering data in opposite
directions
••••• Select IDT Standard timing (using EFA, EFB, FFA, and FFB
flags functions) or First Word Fall Through Timing (using ORA,
ORB, IRA, and IRB flag functions)
••••• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
••••• Serial or parallel programming of partial flags
••••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
••••• Big- or Little-Endian format for word and byte bus sizes
••••• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
••••• Mailbox bypass registers for each FIFO
••••• Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
••••• Auto power down minimizes power dissipation
••••• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
••••• Pin and functionally compatible version of the 5V operating
IDT723624/723634/723644
••••• Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Mail 1
Register
Programmable Flag
Offset Registers
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
10
EFB/ORB
AEB
36
36
FFB/IRB
AFB
B0-B35
FFA/IRA
AFA
SPM
FS0/SD
FS1/
SEN
A0-A35
EFA/ORA
AEA
4664 drw01
36
36
PRS2
PRS1
Timing
Mode
FWFT
36
36
36
36


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn