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IDT72V3624 Datasheet(PDF) 24 Page - Integrated Device Technology

Part # IDT72V3624
Description  3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V3624 Datasheet(HTML) 24 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for
EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of
EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte,
EFB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 16.
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
CSA
W/
RA
MBA
FFA
A0-A35
CLKB
EFB
CSB
W/RB
MBB
ENA
ENB
B0-B35
CLKA
12
4664 drw18
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDS
tDH
tSKEW1
tCLK
tCLKL
tENS2
tENH
tA
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
tCLKH
W1
HIGH
(1)
tREF
tREF


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