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X40430SA Datasheet(PDF) 3 Page - Xicor Inc.

Part # X40430SA
Description  4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor
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Manufacturer  XICOR [Xicor Inc.]
Direct Link  http://www.xicor.com
Logo XICOR - Xicor Inc.

X40430SA Datasheet(HTML) 3 Page - Xicor Inc.

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X40430/X40431 – Preliminary Information
Characteristics subject to change without notice.
3 of 24
REV 1.2.3 11/28/00
www.xicor.com
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
WP
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor.
11
V3MON
V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to VSS or VCC when
not used.
12
V3FAIL
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and
goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin.
13
WDO
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
14
VCC
Supply Voltage
PIN DESCRIPTION (Continued)
Pin
Name
Function
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31 activates a Power
On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40431) and RESET (X40430) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for tPURST there-
after.
VCC
MR
System
Reset
Manual
Reset
X40430
RESET


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