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X40430S14-C Datasheet(PDF) 2 Page - Xicor Inc. |
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X40430S14-C Datasheet(HTML) 2 Page - Xicor Inc. |
2 / 24 page X40430/X40431 – Preliminary Information Characteristics subject to change without notice. 2 of 24 REV 1.2.3 11/28/00 www.xicor.com A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing opera- tion on an I2C bus. The device utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION PIN DESCRIPTION Pin Name Function 1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. 2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. 3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4NC No connect. 5MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. 6 RESET/ RESET RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below VTRIP voltage or if manual reset is asserted. This output stays active for the pro- grammed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. 7VSS Ground V3MON VSS VCC SDA SCL 3 2 4 1 12 13 11 14 LOWLINE NC RESET 7 6 5 8 9 10 V2MON MR WP 3 2 4 1 12 13 11 14 7 6 5 8 9 10 V3FAIL WDO V2FAIL V3MON VCC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL X40430 X40431 14-Pin SOIC, TSSOP 14-Pin SOIC, TSSOP |
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