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X40430S14I-A Datasheet(PDF) 11 Page - Xicor Inc. |
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X40430S14I-A Datasheet(HTML) 11 Page - Xicor Inc. |
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11 / 24 page  X40430/X40431 – Preliminary Information Characteristics subject to change without notice. 11 of 24 REV 1.2.3 11/28/00 www.xicor.com Figure 10. Byte Write Sequence S t a r t S t o p Slave Address Byte Address Data A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the mas- ter begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. Figure 11. Page Write Operation Figure 12. Writing 12 bytes to a 16-byte page starting at location 10. S t a r t S t o p Slave Address Byte Address Data (n) A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 Data (1) A C K (1 ≤ n ≤ 16) address address 10 5 Bytes n-1 7 Bytes address = 6 address pointer ends here Addr = 7 The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowl- edge, and data transfer sequence. |
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