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AM85C30-16BUA Datasheet(PDF) 8 Page - Advanced Micro Devices |
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AM85C30-16BUA Datasheet(HTML) 8 Page - Advanced Micro Devices |
8 / 68 page AMD 8 Am85C30 W/REQA, W/REQB Wait/Request (Outputs; Open drain when pro- grammed for a Wait function, driven High or Low when programmed for a Request function) These dual-purpose outputs may be programmed as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The reset state is Wait. Control A/B Channel A/Channel B Select (Input) This signal selects the channel in which the Read or Write operation occurs. CE Chip Enable (Input; Active Low) This signal selects the SCC for a Read or Write operation. D/C Data/Control Select (Input) This signal defines the type of information transferred to or from the SCC. A High means data is transferred; a Low indicates a command is transferred. Data Bus D7–D0 Data Bus (Input/Output; Three State) These lines carry data and commands to and from the SCC. Interrupt IEI Interrupt Enable In (Input; Active High) IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt-driven device. A High IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO Interrupt Enable Out (Output; Active High) IEO is High only if IEI is High and the CPU is not servic- ing an SCC interrupt or the SCC is not requesting an interrupt (interrupt acknowledge cycle only). IEO is con- nected to the next lower priority device’s IEI input and thus inhibits interrupts from lower priority devices. INT Interrupt Request (Output; Active Low, Open Drain) This signal is activated when the SCC requests an interrupt. INTACK Interrupt Acknowledge (Input; Active Low) This signal indicates an active interrupt acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD becomes active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is latched by the rising edge of PCLK. Serial Data RxDA, RxDB Receive Data (Inputs; Active High) These input signals receive serial data at standard TTL levels. TxDA, TxDB Transmit Data (Outputs; Active High) These output signals transmit serial data at standard TTL levels. Miscellaneous GND Ground PCLK Clock (Input) This is the master SCC clock used to synchronize inter- nal signals. PCLK is not required to have any phase relationship with the master system clock. PCLK is a TTL- level signal. Maximum transmit rate is 1/4 PCLK. VCC + 5 V Power Supply |
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