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IDT74ALVCH16345 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT74ALVCH16345
Description  3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH16345 Datasheet(HTML) 4 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
4
IDT74ALVCH16345
3.3VCMOSREGISTEREDADDRESSLINEDRIVERWITH3-STATEOUTPUTS
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
CPD
PowerDissipationCapacitanceOutputsenabled
CL = 0pF, f = 10Mhz
pF
CPD
PowerDissipationCapacitanceOutputsdisabled
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
V
VCC = 2.3V
IOH = – 6mA
2
VCC = 2.3V
IOH = – 12mA
1.7
VCC = 2.7V
2.2
VCC = 3V
2.4
VCC = 3V
IOH = – 24mA
2
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
0.2
V
VCC = 2.3V
IOL = 6mA
0.4
IOL = 12mA
0.7
VCC = 2.7V
IOL = 12mA
0.4
VCC = 3V
IOL = 24mA
0.55
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. For tSK(b) OUTPUT1
and OUTPUT2 are in the same bank.
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
150
150
150
ns
tPLH
PropagationDelay
1.5
5.4
1.5
4.4
1.5
4
ns
tPHL
CLK to xQx
tPZH
OutputEnableTime
1.5
5.2
1.5
5.1
1.5
4.5
ns
tPZL
OE to xQx
tPHZ
OutputDisableTime
1.5
5.5
1.5
4.5
1.5
5.2
ns
tPLZ
OE to xQx
tSU
Set-up Time, CEx to CLK, HIGH or LOW
1.5
1.5
1.5
ns
tSU
Set-up Time, Dx to CLK, HIGH or LOW
1.5
1.5
1.5
ns
tH
Hold Time, CEx to CLK, HIGH or LOW
0.5
0.5
0.5
ns
tH
Hold Time, Dx to CLK, HIGH or LOW
0.5
0.5
0.5
ns
tW
Pulse Width, CLK HIGH or LOW
3
3
3
ns
tSK(o)
OutputSkew(2)
500
ps
tSK(b)
OutputSkew(2)
350
ps


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