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IDT74ALVCH16903 Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. IDT74ALVCH16903
Description  3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH16903 Datasheet(HTML) 3 Page - Integrated Device Technology

 
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INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
3
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
GND
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
48
49
50
51
52
53
54
55
56
1
GND
GND
CLK
1A
11A/YERREN
OE
1Y1
1Y2
2Y1
2Y2
3Y1
3Y2
4Y1
4Y2
5Y1
5Y2
6Y1
6Y2
7Y1
7Y2
8Y1
8Y2
9Y1
11Y1
11Y2
2A
3A
4A
12A
12Y1
12Y2
5A
6A
7A
APAR
8A
YERR
VCC
9A
GND
VCC
VCC
VCC
24
33
GND
25
27
30
9Y2
10Y1
MODE
10A
PARI/O
GND
10Y2
26
31
32
PAROE
CLKEN
29
28
PARI/O FUNCTION TABLE(1)
Inputs
Output
PAROE
Σ
ΣΣ
ΣΣ OF INPUTS
APAR
PARI/O
1A-10A = H
L
0, 2, 4, 6, 8,10
L
L
L
1, 3, 5, 7, 9
L
H
L
0, 2, 4, 6, 8, 10
H
H
L
1, 3, 5, 7, 9
H
L
HX
X
Z
NOTE:
1. This table applies to the first device of a cascaded pair of ALVCH16903 devices.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Pin Names
I/O
Description
1A-12A
I
Data Inputs(1)
1Y1-12Y2
O
3-StateDataOutputs
CLK
I
Clock Input
CLKEN
I
Clock Enable Input (Active LOW)
MODE
I
Select Pin
YERREN
I
Error Signal Output Enable (Active LOW)
PAROE
I
Parity Output Enable (Active LOW)
PARI/O
I/O
ParityInput/Output
YERR
O
Error Signal (Open Drain)
OE
I
Output Enable Input (Active LOW)
APAR
I
Parity Input
PIN DESCRIPTION


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