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IDT74ALVCH16903 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74ALVCH16903
Description  3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH16903 Datasheet(HTML) 2 Page - Integrated Device Technology

 
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INDUSTRIALTEMPERATURERANGE
2
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
FUNCTIONAL BLOCK DIAGRAM
OE
1
29
28
MODE
33
CLK
56
1A-12A,
APAR
CLKE N
13
13
(9A-12A, APAR)
(1A-11A/Y ERREN, A PAR)
PAR OE
(1A-12A)
12
Flip
Flop
Flip
Flop
Parity
Check
XOR
D
Q
D
Q
D
Q
D
Q
(1A-10A)
10
11
APA R
APAR
(11A/YERR EN)
YER R
PARI/O
30
12
12
36
12
1Y2-12Y2
1Y1-12Y1
(1A-8A)
8
13
13
5
5
FUNCTION TABLE(1)
Inputs
Outputs
OE
MODE
CLKEN
CLK
A
1Yx-8Yx
9Yx-12Yx
LLL
HH
H
LLL
LL
L
LL
H
HY(2)
H
LL
H
LY(2)
L
LH
X
X
H
H
H
LH
X
X
L
L
L
HX
X
X
X
Z
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state conditions were established.
PARITY FUNCTION TABLE(1)
Inputs
Output
OE
PAROE(2)
11A/
PARI/O
Σ
ΣΣ
ΣΣ OF INPUTS APAR YERR
YERREN(3)
1A-10A= H
L
H
L
L
0, 2, 4, 6, 8, 10
L
H
L
H
L
L
1, 3, 5, 7, 9
L
L
L
H
L
L
0, 2, 4, 6, 8, 10
H
L
L
H
L
L
1, 3, 5, 7, 9
H
H
L
H
L
H
0, 2, 4, 6, 8, 10
L
L
L
H
L
H
1, 3, 5, 7, 9
L
H
L
H
L
H
0, 2, 4, 6, 8, 10
H
H
L
H
L
H
1, 3, 5, 7, 9
H
L
HX
X
X
X
X
H
LX
H
X
X
X
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. When used as a single device, PAROE must be tied HIGH.
3. Valid after appropriate number of clock pulses have set internal register.


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