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74HC237 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74HC237
Description  3-to-8 line decoder/demultiplexer with address latches
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74HC237 Datasheet(HTML) 2 Page - NXP Semiconductors

   
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December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with
address latches
74HC/HCT237
FEATURES
• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent
controls
• Active HIGH mutually exclusive outputs
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT237 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (An). The “237”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “237” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E1 and E2) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E2
is HIGH.
The “237” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL / tPLH
propagation delay
CL = 15 pF; VCC =5 V
An to Yn
16
19
ns
LE to Yn
19
21
ns
E1 to Yn
14
17
ns
E2 to Yn
14
17
ns
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
60
63
pF


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