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LTC2422 Datasheet(PDF) 19 Page - Linear Technology |
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LTC2422 Datasheet(HTML) 19 Page - Linear Technology |
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19 / 32 page  19 LTC2421/LTC2422 24212f A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conver- sion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 11. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the ex- ternal SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then imme- diately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is out- put to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. Figure 10. Internal Serial Clock, Reduced Data Output Length APPLICATIO S I FOR ATIO VCC 10k VCC FO FSSET ZSSET SCK CH1 SDO GND CS REFERENCE VOLTAGE ZSSET + 0.1V TO VCC 0V TO FSSET – 100mV CH0 = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 1 µF 110 9 8 7 6 2 3 4 5 2.7V TO 5.5V LTC2422 VCC ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET – ZSSET) SDO SCK (INTERNAL) CS >tEOCtest MSB EXR SIG BIT 8 TEST EOC TEST EOC BIT 19 BIT 18 BIT 20 BIT 21 BIT 22 EOC CH0/CH1 BIT 23 EOC BIT 0 SLEEP DATA OUTPUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DATA OUTPUT CONVERSION CONVERSION SLEEP 24212 F10 <tEOCtest TEST EOC |
Similar Part No. - LTC2422 |
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Similar Description - LTC2422 |
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