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CY7C453-14JI Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C453-14JI
Description  512x9 2Kx9 and 4Kx9 Cascadable Clocked FIFOs with Programmable
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C453-14JI Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A
Page 7 of 24
Switching Waveforms
Notes:
18. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW.
19. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW.
20. All data outputs (Q0 – 8) go LOW as a result of the rising edge of MR after tAMR.
21. In this example, Q0 – 8 will remain valid until tOHMR if either the first read shown did not occur or if the read occurred soon enough such that the valid
data was caused by it.
Write Clock Timing Diagram
Read Clock Timing Diagram
tCKW
C451-6
C451-7
tCKH
tCKL
tHD
tSD
ENABLED WRITE
DISABLED WRITE
VALID DATA IN
tSEN
tHEN
tSEN
tHEN
ENABLED READ
DISABLED READ
PREVIOUS WORD
tCKR
tCKH
tCKL
tOH
tSEN
tHEN
tSEN
tHEN
NEW WORD
tA
Master Reset (Default with Free-Running Clocks) Timing Diagram
tPMR
tMRR
tSCMR
tMRR
tOHMR
VALID DATA
tAMR
tMRF
ALL DATA
OUTPUTS LOW
tSCMR
tMRF
CKW
MR
ENW
CKR
ENR
Q0 – 8
E/F,PAFE
HF
FIRST
WRITE
tFH
tFH
tFH
tFD
tFD
tFH
tFH
tFD
tFD
tFH
CKR
Q0 – 8
ENR
E/F,PAFE
CKW
D0 – 8
ENW
E/F, PAFE,HF
[18,19,20,21]


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