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CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A
Page 9 of 24
Notes:
22. “Count” is the number of words in the FIFO.
23. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
24. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes
W3 in the flag update.
25. CKR is clock; CKW is opposite clock.
26. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs greater than tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty
state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count
or the FIFO’s data outputs.
Switching Waveforms (continued)
Read to Empty Timing Diagram with Free-Running Clocks
LATENTCYCLE
tSKEW1
tSKEW2
tFD
tFD
tFD
COUNT
1
0
1
0
ENABLED
READ
FLAG
UPDATE
ENABLED
READ
IGNORED
READ
ENABLED
WRITE
IGNORED
READ
IGNORED
READ
READ
CKR
ENR
CKW
ENW
PAFE
E/F
HF
C451-11
HIGH
LOW
Read to Empty Timing Diagram
COUNT
32
0
1 (NO CHANGE)
tFD
tFD
R1
ENABLED
FLAG
UPDATE
11
0
LATENTCYCLE
READ
ENABLED
WRITE
tSKEW2
tSKEW1
CKW
ENR
ENW
E/F
CKR
LOW
tFD
C451-12
READ
R2
ENABLED
READ
R3
ENABLED
READ
R5
ENABLED
READ
R4
W1
R1
R2
R3
R4
R5
R6
W1
W2
W4
W5
W6
W3
tSKEW2
PAFE
LOW
[22,25,26]
[22,23,24,25]
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