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STE2001 Datasheet(PDF) 8 Page - STMicroelectronics |
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STE2001 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 36 page STE2001 8/36 Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0) Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1) Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1) BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 0123 124 125 126 127 D00IN1138 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 0 1 2 3 124 125 126 127 D00IN1139 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 127 126 125 124 3210 D00IN1140 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 127 126 125 124 3 2 1 0 D00IN1141 |
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