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74HC174 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74HC174
Description  Hex D-type flip-flop with reset; positive-edge trigger
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74HC174 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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1998 Jul 08
2
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
FEATURES
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb=25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
CP to Qn
17
18
ns
MR to Qn
13
17
ns
fmax
maximum clock frequency
99
69
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation
capacitance per flip-flop
notes 1 and 2
17
17
pF


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