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EM6821 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA |
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EM6821 Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA |
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2 / 68 page 
R EM6821 Copyright © 2005, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com EM6821 at a glance • Power Supply - Low voltage low power architecture including internal voltage regulator - 1.2 ... 3.6 V battery voltage - 1.3 µA in active mode (Xtal, LCD on, 25 °C) - 0.4 µA in standby mode (Xtal, LCD off, 25 °C) - 0.1 µA in sleep mode (25 °C) - 32 KHz Oscillator • RAM - 64 x 4 bit, direct addressable - 64 x 4 bit, indexed addressable • ROM - 4k x 16 bit, metal mask programmable • CPU - 4-bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions • Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in halt) - Sleep mode (no clock, reset state) - Initial reset on power on (POR) - Watchdog reset (logic and oscillation watchdogs) - Reset terminal - Reset with input combination on port A (register selectable) • Prescaler - 15 stage system clock divider down to 1Hz - 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink - Prescaler reset (4kHz to 1Hz) • Liquid Crystal Display Driver (LCD) - 20 Segments 3 or 4 times multiplexed - Internal or external voltage multiplier - Free Segment allocation architecture (metal 2 mask) - LCD switch off for power save • 8-Bit Serial Interface - 3 wire (Clock, DataIn , DataOut) master/slave mode - READY output during data transfer - Maximum shift clock is equal to the main system clock - Interrupt request to the CPU after 8 bits data transfer - Supports different serial formats - Can be configured as a parallel 4 bit input/output port - Direct input read on the port terminals - All outputs can be put tristate (default) - Selectable pull-downs in input mode - CMOS or Nch. open drain outputs - Weak pull-up selectable in Nch. open drain mode • 4-Bit Input Port A - Direct input read on the port terminals - Debouncer function available on all inputs - Interrupt request on positive or negative edge - Pull-up or pull-down or none selectable by register - Test variables (software) for conditional jumps - PA[0] and PA[3] are inputs for the event counter - PA[3] is Start/Stop input for the millisecond counter - Reset with input combination (register selectable) • 4-Bit Bi-directional Port B - All different functions bit-wise selectable - Direct input read on the port terminals - Data output latches - CMOS or Nch. open drain outputs - Pull-down or pull-up selectable - Weak pull-up in Nch. open drain mode - Selectable PWM, 32kHz, 1kHz and 1Hz output • Melody Generator - Dedicated Buzzer terminal - 7 tones plus silence output - The output can be put tristate (default) - Internal 4-bit timer, usable also in standalone mode - 4 different timer input clocks - Timer with automatic reload or single run - Timer interrupt request when reaching 0 • Voltage Level Detector (SVLD) - 8 different levels from 1.2 V to 4.0 V. - Busy flag during measure • 10-Bit Universal Counter - 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[0] or PA[3]) - 8 different input clocks- - Full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - Hi-frequency input on PA[3] and PA[0] - Pulse width modulation (PWM) output • Millisecond Counter - 3 digits binary coded decimal counter (12 bits) - PA[3] input signal pulse width and period measurement - Internal 1000 Hz clock generation - Hardware or software controlled start stop mode - Interrupt request on either 1/10 Sec or 1Sec • Interrupt Controller - 5 external and 8 internal interrupt request sources - Each interrupt request can individually be masked - Each interrupt flag can individually be reset - Automatic reset of each interrupt request after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode. |
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