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EM6640 Datasheet(PDF) 6 Page - EM Microelectronic - MARIN SA |
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EM6640 Datasheet(HTML) 6 Page - EM Microelectronic - MARIN SA |
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6 / 62 page 
EM6640 03/02 REV. C/446 Copyright 2002, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com The output drivers are supplied directly from the external supply VDD. 4. Reset Figure 5 illustrates the reset structure of the EM6640. One can see that there are six possible reset sources: (1) Internal initial reset from the Power On Reset (POR) circuitry. (2) External reset by simultaneous high/low inputs to PortA. (Combinations are defined in the registers OptInpRSel1 and OptInpRSel2 (3) Internal reset from the Digital Watchdog. (4) Internal reset from the Oscillation Detection Circuit. (5) Internal reset when SLEEP mode is activated. (6) Internal reset from Sleep Counter Reset. All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the System Reset remains active long enough for all system functions to be reset (active for N SysClk cycles). The ‘CPU Reset Delay‘ ensures that the Reset CPU remains active until the oscillator is in stable oscillation. As well as activating the System Reset and the Reset CPU, the POR also resets all Option Registers and the SLEEP ENABLE latch. System Reset and Reset CPU do not reset Option Registers nor the SLEEP ENABLE latch. Figure 5. Reset structure Digital W atchdog O scillation Detection System Reset Reset from PortA Input com bination NoInpReset Sleep Inhibit O scillation detection Inhibit Digital W atchdog POR PO R to O ption Registers & S LEEP ENAB LE latch SLE EP Latch SLEEP ENABLE Latch DEB O UNCE R (for reset) A nalog Debouncer PO R Internal Data Bus Write Reset Read Status Write Activ e Read Status CK[10] CK[1] ck[10] S ystem Reset Delay Reset CP U CPU Reset Delay ck[11] ck[18] Reset set R R Sleep Counter Reset EN Sleep Inhibit SCR |
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