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W83C554F Datasheet(PDF) 89 Page - Winbond |
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W83C554F Datasheet(HTML) 89 Page - Winbond |
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89 / 156 page  W83C554F Register Information WINBOND ELECTRONICS CORP. AMERICA 87 Scatter/Gather Registers Scatter/Gather (S/G) provides the capability of transferring multiple buffers between memory (ISA/PCI) and I/O (ISA DMA device) without CPU intervention. In Scatter/Gather the DMA can read the memory address and word count from an array of buffer descriptors located in system memory (PCI only), called the Scatter/Gather Descriptor (SGD) table. This allows the DMA controller to sustain DMA transfers until all of the buffers in the SGD table are transferred. Software prepares a SGD table in system memory. Each SGD is 8-bytes long and consists of an address pointer to the starting address and the byte count (number of bytes) of the memory buffer to be transferred. In any given SGD table, two consecutive SGDs are offset by 8-bytes and are aligned on a 4-byte boundary. Each SGD is defined below. For an 8-bit DMA I/O device: For a 16-bit DMA I/O device, bit 0 of the Memory Buffer Starting Address and byte count must be 0. Bit 31 of Dword 1 is the end of Link Flag. Bus master operation terminates upon completion of the description entry that has EOL set. The SGD table cannot cross a 64k memory boundary. The addresses of all of the registers located from 43Fh to 40Ah (except 40Bh) are relocatable by programming the Scatter/Gather Relocation Base Address Register (Function 0, address 41h) in the PCI Configuration Space. These registers are marked with an asterisk (*). |
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